1. Field of the Invention
This invention relates generally to a method of filling a cavity with a conductive material. More particularly, this invention relates to a method of filling a cavity in regions of a semiconductor wafer wherein electrical wiring are to be made. Even more particularly, this invention relates to a method of filling a cavity with a conductive material such gold, copper, tungsten and nickel.
2. Discussion of the Related Art
The increased demand for higher performance semiconductor devices has required the density of metallization lines to be increased and in addition has required the addition of stacked layers. These requirements have necessitated the development of novel approaches in the methods of forming interconnections that not only integrate fine geometry definition but are also conducive to subsequent CMP (chemical mechanical polishing) processing. As the interconnection line widths shrink, the challenges of etching material using photoresist-as-mask techniques have become increasingly difficult.
Traditional methods of forming interconnection structures include the use of photoresist patterning and chemical or plasma "subtractive" etching as the primary metal-patterning technique. However, as the geometry of the semiconductor circuits continues to decrease, traditional interconnection materials are unsuitable. For example, aluminum interconnections with reduced line width results in greater resistance and heat. The increased heat causes the aluminum to melt. The use of copper, gold, silver and nickel is called for because they have low resistance and thinner lines can be used without detrimental heating. Additional difficulties in the traditional method include the trapping of impurities or volatile materials, such as aluminum chloride, in the inter-wiring spaces, which may pose reliability risks to the device, leaving residual metal stringers, which may cause electrical shorts, residual photoresist, and poor step coverage. These problems contribute to low yields and necessitate relaxed design rules that result in low layout density.
Current integrated circuit devices with multiple levels of wiring require conductive material to be filled into small trenches or vias. One favorite technique employs a global deposition or sputtering of the conductive material over the entire surface of the wafer. A blanket etch back process removes the unwanted material from the non-trench or non-via regions leaving the trenches or vias filled with the conductive material. The disadvantages of this method are poor step coverage, residual conductive material left in the non-trench regions, and relatively large recessions or dimples directly above the trench or via areas.
A newer technique to eliminate the above problems utilizes a chemical mechanical polish (CMP) after the global deposition or plating of conductive material. Although this method works well with some metals, such as aluminum and tungsten, too much waste is involved. Moreover, aluminum is not easily polished with a chemical mechanical polish process because it is a relatively soft material that molts onto the harder oxide. This leaves large amounts of aluminum in the non-trench region and causes the device to short. In some cases, the topography is so extreme that a reverse mask process must be used to protect the recessed areas and an isotropic etch is utilized to reduce the peaks over the non-trench regions so that the CMP process can achieve a uniform surface. Since it is difficult to dry etch non-aluminum metals, a corrosive (acid) or a reverse plating method with a reverse mask is used to remove the peaks. All of these complicate the process.
Therefore, what is needed is a method to fill cavities in semiconductor wafers with a conductive material that does not require extensive polishing if any at all.